CWE-1224 Base Incomplete

Improper Restriction of Write-Once Bit Fields

This vulnerability occurs when hardware write-once protection mechanisms, often called 'sticky bits,' are incorrectly implemented, allowing software to reprogram them multiple times.

Definition

What is CWE-1224?

This vulnerability occurs when hardware write-once protection mechanisms, often called 'sticky bits,' are incorrectly implemented, allowing software to reprogram them multiple times.

Hardware designs use special write-once or 'sticky' bit fields in control registers to lock critical settings. These are intended to be configured only once—typically during initial boot by trusted firmware—and then become permanently read-only. This mechanism is a fundamental security feature that prevents runtime software or malware from altering secure hardware configurations, such as memory protection or debug access controls. When this restriction fails, software can repeatedly overwrite these bits. A common implementation flaw is creating 'write-1-once' logic instead of true 'write-once' protection. In this flawed scenario, a bit might only become locked after being set to '1,' leaving it vulnerable if set to '0' first or allowing toggling between values. This exposes the hardware to privilege escalation, system compromise, or bypass of critical security boundaries.

Real-world impact

Real-world CVEs caused by CWE-1224

No public CVE references are linked to this CWE in MITRE's catalog yet.

How attackers exploit it

Step-by-step attacker path

1
Identify a code path that handles untrusted input without validation.
2
Craft a payload that exercises the unsafe behavior — injection, traversal, overflow, or logic abuse.
3
Deliver the payload through a normal request and observe the application's reaction.
4
Iterate until the response leaks data, executes attacker code, or escalates privileges.

Vulnerable code example

Vulnerable Verilog

Consider the example design module system verilog code shown below. register_write_once_example module is an example of register that has a write-once field defined. Bit 0 field captures the write_once_status value. This implementation can be for a register that is defined by specification to be a write-once register, since the write_once_status field gets written by input data bit 0 on first write.

Vulnerable Verilog

module register_write_once_example
 ( 
 input [15:0] Data_in, 
 input Clk, 
 input ip_resetn, 
 input global_resetn,
 input write,
 output reg [15:0] Data_out 
 );

 reg Write_once_status; 

 always @(posedge Clk or negedge ip_resetn)

```
   if (~ip_resetn)
   begin
  	 Data_out <= 16'h0000;
  	 Write_once_status <= 1'b0; 
   end 
   else if (write & ~Write_once_status)
   begin
  	 Data_out <= Data_in & 16'hFFFE;
  	 Write_once_status <= Data_in[0]; // Input bit 0 sets Write_once_status
   end
   else if (~write)
   begin 
  	 Data_out[15:1] <= Data_out[15:1]; 
  	 Data_out[0] <= Write_once_status; 
   end 
 endmodule

Secure code example

Secure Verilog

The above example only locks further writes if write_once_status bit is written to one. So it acts as write_1-Once instead of the write-once attribute.

Secure Verilog

module register_write_once_example 
 ( 
 input [15:0] Data_in, 
 input Clk, 
 input ip_resetn, 
 input global_resetn, 
 input write, 
 output reg [15:0] Data_out 
 ); 

 reg Write_once_status; 

 always @(posedge Clk or negedge ip_resetn) 

```
   if (~ip_resetn) 
   begin 
  	 Data_out <= 16'h0000; 
  	 Write_once_status <= 1'b0; 
   end 
   else if (write & ~Write_once_status) 
   begin 
  	 Data_out <= Data_in & 16'hFFFE; 
  	 Write_once_status <= 1'b1; // Write once status set on first write, independent of input 
   end 
   else if (~write) 
   begin 
  	 Data_out[15:1] <= Data_out[15:1]; 
  	 Data_out[0] <= Write_once_status; 
   end 
 endmodule

What changed: the unsafe sink is replaced (or the input is validated/escaped) so the same payload no longer triggers the weakness.

Prevention checklist

How to prevent CWE-1224

Architecture and Design During hardware design all register write-once or sticky fields must be evaluated for proper configuration.
Testing The testing phase should use automated tools to test that values are not reprogrammable and that write-once fields lock on writing zeros.

Detection signals

How to detect CWE-1224

SAST High

Run static analysis (SAST) on the codebase looking for the unsafe pattern in the data flow.

DAST Moderate

Run dynamic application security testing against the live endpoint.

Runtime Moderate

Watch runtime logs for unusual exception traces, malformed input, or authorization bypass attempts.

Code review Moderate

Code review: flag any new code that handles input from this surface without using the validated framework helpers.

Plexicus auto-fix

Plexicus auto-detects CWE-1224 and opens a fix PR in under 60 seconds.

Codex Remedium scans every commit, identifies this exact weakness, and ships a reviewer-ready pull request with the patch. No tickets. No hand-offs.

Get a demo Try Plexicus free

Frequently asked questions

What is CWE-1224?

This vulnerability occurs when hardware write-once protection mechanisms, often called 'sticky bits,' are incorrectly implemented, allowing software to reprogram them multiple times.

How serious is CWE-1224?

MITRE has not published a likelihood-of-exploit rating for this weakness. Treat it as medium-impact until your threat model proves otherwise.

What languages or platforms are affected by CWE-1224?

MITRE lists the following affected platforms: Verilog, VHDL, System on Chip.

How can I prevent CWE-1224?

During hardware design all register write-once or sticky fields must be evaluated for proper configuration. The testing phase should use automated tools to test that values are not reprogrammable and that write-once fields lock on writing zeros.

How does Plexicus detect and fix CWE-1224?

Plexicus's SAST engine matches the data-flow signature for CWE-1224 on every commit. When a match is found, our Codex Remedium agent opens a fix PR with the corrected code, tests, and a one-line summary for the reviewer.

Where can I learn more about CWE-1224?

MITRE publishes the canonical definition at https://cwe.mitre.org/data/definitions/1224.html. You can also reference OWASP and NIST documentation for adjacent guidance.

Related weaknesses

Weaknesses related to CWE-1224

CWE-284 Parent

Don't Let Security
Weigh You Down.

Stop choosing between AI velocity and security debt. Plexicus is the only platform that runs Vibe Coding Security and ASPM in parallel — one workflow, every codebase.

Get started free Book a demo

Improper Restriction of Write-Once Bit Fields

What is CWE-1224?

Real-world CVEs caused by CWE-1224

Step-by-step attacker path

Vulnerable Verilog

Secure Verilog

How to prevent CWE-1224

How to detect CWE-1224

Plexicus auto-detects CWE-1224 and opens a fix PR in under 60 seconds.

Frequently asked questions

Weaknesses related to CWE-1224

Improper Access Control

On-Chip Debug and Test Interface With Improper Access Control

Insufficient Granularity of Access Control

Improper Prevention of Lock Bit Modification

Security-Sensitive Hardware Controls with Missing Lock Bit Protection

CPU Hardware Not Configured to Support Exclusivity of Write and Execute Operations

Improper Access Control Applied to Mirrored or Aliased Memory Regions

Improper Restriction of Security Token Assignment

Improper Handling of Overlap Between Protected Memory Ranges

Further reading

Don't Let Security
Weigh You Down.

Improper Restriction of Write-Once Bit Fields

What is CWE-1224?

Real-world CVEs caused by CWE-1224

Step-by-step attacker path

Vulnerable Verilog

Secure Verilog

How to prevent CWE-1224

How to detect CWE-1224

Plexicus auto-detects CWE-1224 and opens a fix PR in under 60 seconds.

Frequently asked questions

Weaknesses related to CWE-1224

Improper Access Control

On-Chip Debug and Test Interface With Improper Access Control

Insufficient Granularity of Access Control

Improper Prevention of Lock Bit Modification

Security-Sensitive Hardware Controls with Missing Lock Bit Protection

CPU Hardware Not Configured to Support Exclusivity of Write and Execute Operations

Improper Access Control Applied to Mirrored or Aliased Memory Regions

Improper Restriction of Security Token Assignment

Improper Handling of Overlap Between Protected Memory Ranges

Further reading

Don't Let SecurityWeigh You Down.

Don't Let Security
Weigh You Down.