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CWE-1239 Variant Draft
Improper Zeroization of Hardware Register
This vulnerability occurs when a hardware component fails to properly erase sensitive data from its internal registers before a new user or process gains access to the hardware block.
Definition
What is CWE-1239?
This vulnerability occurs when a hardware component fails to properly erase sensitive data from its internal registers before a new user or process gains access to the hardware block.
Hardware blocks, like cryptographic accelerators, use built-in registers to temporarily hold data during operations. These registers can retain sensitive information such as encryption keys or passwords, which becomes a security risk if not cleared. When control of the hardware switches—for example, during a mode change or between different software processes—the next entity accessing the registers might be able to read the previous user's leftover data.
To prevent data leaks, hardware must actively clear its registers during user transitions or when a physical tamper event is detected. This clearing process, often called zeroization, is a critical security requirement in standards like FIPS-140-2 for ensuring that sensitive data isn't exposed unintentionally.
Real-world impact
Real-world CVEs caused by CWE-1239
No public CVE references are linked to this CWE in MITRE's catalog yet.
How attackers exploit it
Step-by-step attacker path
- 1
Suppose a hardware IP for implementing an encryption routine works as expected, but it leaves the intermediate results in some registers that can be accessed. Exactly why this access happens is immaterial - it might be unintentional or intentional, where the designer wanted a "quick fix" for something.
- 2
The example code below [REF-1379] is taken from the SHA256 Interface/wrapper controller module of the HACK@DAC'21 buggy OpenPiton SoC. Within the wrapper module there are a set of 16 memory-mapped registers referenced data[0] to data[15]. These registers are 32 bits in size and are used to store the data received on the AXI Lite interface for hashing. Once both the message to be hashed and a request to start the hash computation are received, the values of these registers will be forwarded to the underlying SHA256 module for processing. Once forwarded, the values in these registers no longer need to be retained. In fact, if not cleared or overwritten, these sensitive values can be read over the AXI Lite interface, potentially compromising any previously confidential data stored therein.
- 3
In the previous code snippet [REF-1379] there is the lack of a data clearance mechanism for the memory-mapped I/O registers after their utilization. These registers get cleared only when a reset condition is met. This condition is met when either the global negative-edge reset input signal (rst_ni) or the dedicated reset input signal for SHA256 peripheral (rst_3) is active. In other words, if either of these reset signals is true, the registers will be cleared. However, in cases where there is not a reset condition these registers retain their values until the next hash operation. It is during the time between an old hash operation and a new hash operation that that data is open to unauthorized disclosure.
- 4
To correct the issue of data persisting between hash operations, the memory mapped I/O registers need to be cleared once the values written in these registers are propagated to the SHA256 module. This could be done for example by adding a new condition to zeroize the memory mapped I/O registers once the hash value is computed, i.e., hashValid signal asserted, as shown in the good code example below [REF-1380]. This fix will clear the memory-mapped I/O registers after the data has been provided as input to the SHA engine.
Vulnerable code example
Vulnerable Verilog
The example code below [REF-1379] is taken from the SHA256 Interface/wrapper controller module of the HACK@DAC'21 buggy OpenPiton SoC. Within the wrapper module there are a set of 16 memory-mapped registers referenced data[0] to data[15]. These registers are 32 bits in size and are used to store the data received on the AXI Lite interface for hashing. Once both the message to be hashed and a request to start the hash computation are received, the values of these registers will be forwarded to the underlying SHA256 module for processing. Once forwarded, the values in these registers no longer need to be retained. In fact, if not cleared or overwritten, these sensitive values can be read over the AXI Lite interface, potentially compromising any previously confidential data stored therein.
...
```
// Implement SHA256 I/O memory map interface
// Write side
always @(posedge clk_i)
begin
if(~(rst_ni && ~rst_3))
begin
startHash <= 0;
newMessage <= 0;
data[0] <= 0;
data[1] <= 0;
data[2] <= 0;
...
data[14] <= 0;
data[15] <= 0;
... Secure code example
Secure Verilog
To correct the issue of data persisting between hash operations, the memory mapped I/O registers need to be cleared once the values written in these registers are propagated to the SHA256 module. This could be done for example by adding a new condition to zeroize the memory mapped I/O registers once the hash value is computed, i.e., hashValid signal asserted, as shown in the good code example below [REF-1380]. This fix will clear the memory-mapped I/O registers after the data has been provided as input to the SHA engine.
...
```
// Implement SHA256 I/O memory map interface
// Write side
always @(posedge clk_i)
begin
if(~(rst_ni && ~rst_3))
begin
startHash <= 0;
newMessage <= 0;
data[0] <= 0;
data[1] <= 0;
data[2] <= 0;
...
data[14] <= 0;
data[15] <= 0;
end
```
else if(hashValid && ~hashValid_r)**
```
```
begin**
```
```
data[0] <= 0;**
**data[1] <= 0;**
**data[2] <= 0;**
**...**
**data[14] <= 0;**
**data[15] <= 0;**
end
... What changed: the unsafe sink is replaced (or the input is validated/escaped) so the same payload no longer triggers the weakness.
Prevention checklist
How to prevent CWE-1239
- Architecture and Design Every register potentially containing sensitive information must have a policy specifying how and when information is cleared, in addition to clarifying if it is the responsibility of the hardware logic or IP user to initiate the zeroization procedure at the appropriate time.
Detection signals
How to detect CWE-1239
Run dynamic application security testing against the live endpoint.
Watch runtime logs for unusual exception traces, malformed input, or authorization bypass attempts.
Code review: flag any new code that handles input from this surface without using the validated framework helpers.
Plexicus auto-detects CWE-1239 and opens a fix PR in under 60 seconds.
Codex Remedium scans every commit, identifies this exact weakness, and ships a reviewer-ready pull request with the patch. No tickets. No hand-offs.
Frequently asked questions What is CWE-1239?
How serious is CWE-1239?
What languages or platforms are affected by CWE-1239?
How can I prevent CWE-1239?
How does Plexicus detect and fix CWE-1239?
Where can I learn more about CWE-1239?
Frequently asked questions
What is CWE-1239?
This vulnerability occurs when a hardware component fails to properly erase sensitive data from its internal registers before a new user or process gains access to the hardware block.
How serious is CWE-1239?
MITRE has not published a likelihood-of-exploit rating for this weakness. Treat it as medium-impact until your threat model proves otherwise.
What languages or platforms are affected by CWE-1239?
MITRE lists the following affected platforms: Not OS-Specific, Not Architecture-Specific, System on Chip.
How can I prevent CWE-1239?
Every register potentially containing sensitive information must have a policy specifying how and when information is cleared, in addition to clarifying if it is the responsibility of the hardware logic or IP user to initiate the zeroization procedure at the appropriate time.
How does Plexicus detect and fix CWE-1239?
Plexicus's SAST engine matches the data-flow signature for CWE-1239 on every commit. When a match is found, our Codex Remedium agent opens a fix PR with the corrected code, tests, and a one-line summary for the reviewer.
Where can I learn more about CWE-1239?
MITRE publishes the canonical definition at https://cwe.mitre.org/data/definitions/1239.html. You can also reference OWASP and NIST documentation for adjacent guidance.
Related weaknesses
Weaknesses related to CWE-1239
CWE-226 Parent
Sensitive Information in Resource Not Removed Before Reuse
This vulnerability occurs when a system releases a resource like memory or a file for reuse but fails to erase the sensitive data it…
CWE-1272 Sibling
Sensitive Information Uncleared Before Debug/Power State Transition
This vulnerability occurs when a device changes its power mode or enters a debug state but fails to wipe sensitive data that should become…
CWE-1301 Sibling
Insufficient or Incomplete Data Removal within Hardware Component
The product's data removal process fails to completely erase all data from hardware components, potentially leaving sensitive information…
CWE-1342 Sibling
Information Exposure through Microarchitectural State after Transient Execution
This vulnerability occurs when a CPU fails to completely erase temporary data traces left behind by speculative execution or error…
CWE-244 Sibling
Improper Clearing of Heap Memory Before Release ('Heap Inspection')
Using realloc() to resize buffers containing secrets like passwords or keys can leave that sensitive data exposed in memory, as the…
Resources
Further reading
- MITRE — official CWE-1239 https://cwe.mitre.org/data/definitions/1239.html
- FIPS PUB 140-2: SECURITY REQUIREMENTS FOR CRYPTOGRAPHIC MODULES https://csrc.nist.gov/files/pubs/fips/140-2/upd2/final/docs/fips1402.pdf
- Data Remanence in Semiconductor Devices https://www.usenix.org/legacy/events/sec01/full_papers/gutmann/gutmann.pdf
- sha256_wrapper.sv https://github.com/HACK-EVENT/hackatdac21/blob/b9ecdf6068445d76d6bee692d163fededf7a9d9b/piton/design/chip/tile/ariane/src/sha256/sha256_wrapper.sv#L94-L116
- Fix for sha256_wrapper.sv https://github.com/HACK-EVENT/hackatdac21/blob/e8ba396b5c7cec9031e0e0e18ac547f32cd0ed50/piton/design/chip/tile/ariane/src/sha256/sha256_wrapper.sv#L98C1-L139C18
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