CWE-1298 Base Draft

Hardware Logic Contains Race Conditions

A hardware race condition occurs when security-critical logic circuits receive signals at slightly different times, creating temporary glitches that can bypass system protections.

Definition

What is CWE-1298?

A hardware race condition occurs when security-critical logic circuits receive signals at slightly different times, creating temporary glitches that can bypass system protections.

In hardware design, race conditions happen when signals from the same source take different paths through logic gates and arrive at slightly different times. This timing mismatch can cause a gate's output to flicker into an incorrect state—a glitch—before settling correctly. These glitches, though often brief, create a window where the hardware operates in an unintended state. When these timing errors occur in security-sensitive circuits like access control modules or cryptographic state machines, they become critical vulnerabilities. Attackers can deliberately trigger or amplify these glitches to bypass authentication, escalate privileges, or leak protected data, effectively undermining the hardware's security guarantees.

Real-world impact

Real-world CVEs caused by CWE-1298

No public CVE references are linked to this CWE in MITRE's catalog yet.

How attackers exploit it

Step-by-step attacker path

1
The code below shows a 2x1 multiplexor using logic gates. Though the code shown below results in the minimum gate solution, it is disjoint and causes glitches.
2
The buggy line of code, commented above, results in signal 'z' periodically changing to an unwanted state. Thus, any logic that references signal 'z' may access it at a time when it is in this unwanted state. This line should be replaced with the line shown below in the Good Code Snippet which results in signal 'z' remaining in a continuous, known, state. Reference for the above code, along with waveforms for simulation can be found in the references below.
3
This line of code removes the glitch in signal z.
4
The example code is taken from the DMA (Direct Memory Access) module of the buggy OpenPiton SoC of HACK@DAC'21. The DMA contains a finite-state machine (FSM) for accessing the permissions using the physical memory protection (PMP) unit. PMP provides secure regions of physical memory against unauthorized access. It allows an operating system or a hypervisor to define a series of physical memory regions and then set permissions for those regions, such as read, write, and execute permissions. When a user tries to access a protected memory area (e.g., through DMA), PMP checks the access of a PMP address (e.g., pmpaddr_i) against its configuration (pmpcfg_i). If the access violates the defined permissions (e.g., CTRL_ABORT), the PMP can trigger a fault or an interrupt. This access check is implemented in the pmp parametrized module in the below code snippet. The below code assumes that the state of the pmpaddr_i and pmpcfg_i signals will not change during the different DMA states (i.e., CTRL_IDLE to CTRL_DONE) while processing a DMA request (via dma_ctrl_reg). The DMA state machine is implemented using a case statement (not shown in the code snippet).
5
However, the above code [REF-1394] allows the values of pmpaddr_i and pmpcfg_i to be changed through DMA's input ports. This causes a race condition and will enable attackers to access sensitive addresses that the configuration is not associated with. Attackers can initialize the DMA access process (CTRL_IDLE) using pmpcfg_i for a non-privileged PMP address (pmpaddr_i). Then during the loading state (CTRL_LOAD), attackers can replace the non-privileged address in pmpaddr_i with a privileged address without the requisite authorized access configuration. To fix this issue (see [REF-1395]), the value of the pmpaddr_i and pmpcfg_i signals should be stored in local registers (pmpaddr_reg and pmpcfg_reg at the start of the DMA access process and the pmp module should reference those registers instead of the signals directly. The values of the registers can only be updated at the start (CTRL_IDLE) or the end (CTRL_DONE) of the DMA access process, which prevents attackers from changing the PMP address in the middle of the DMA access process.

Vulnerable code example

Vulnerable Verilog

The code below shows a 2x1 multiplexor using logic gates. Though the code shown below results in the minimum gate solution, it is disjoint and causes glitches.

Vulnerable Verilog

// 2x1 Multiplexor using logic-gates

 module glitchEx(

```
   input wire in0, in1, sel,
   output wire z
 );
 wire not_sel;
 wire and_out1, and_out2;
 assign not_sel = ~sel;
 assign and_out1 = not_sel & in0;
 assign and_out2 = sel & in1;
 // Buggy line of code:
 assign z = and_out1 | and_out2; // glitch in signal z
 endmodule

Secure code example

Secure Verilog

The buggy line of code, commented above, results in signal 'z' periodically changing to an unwanted state. Thus, any logic that references signal 'z' may access it at a time when it is in this unwanted state. This line should be replaced with the line shown below in the Good Code Snippet which results in signal 'z' remaining in a continuous, known, state. Reference for the above code, along with waveforms for simulation can be found in the references below.

Secure Verilog

assign z <= and_out1 or and_out2 or (in0 and in1);

What changed: the unsafe sink is replaced (or the input is validated/escaped) so the same payload no longer triggers the weakness.

Prevention checklist

How to prevent CWE-1298

Architecture and Design Adopting design practices that encourage designers to recognize and eliminate race conditions, such as Karnaugh maps, could result in the decrease in occurrences of race conditions.
Implementation Logic redundancy can be implemented along security critical paths to prevent race conditions. To avoid metastability, it is a good practice in general to default to a secure state in which access is not given to untrusted agents.

Detection signals

How to detect CWE-1298

SAST High

Run static analysis (SAST) on the codebase looking for the unsafe pattern in the data flow.

DAST Moderate

Run dynamic application security testing against the live endpoint.

Runtime Moderate

Watch runtime logs for unusual exception traces, malformed input, or authorization bypass attempts.

Code review Moderate

Code review: flag any new code that handles input from this surface without using the validated framework helpers.

Plexicus auto-fix

Plexicus auto-detects CWE-1298 and opens a fix PR in under 60 seconds.

Codex Remedium scans every commit, identifies this exact weakness, and ships a reviewer-ready pull request with the patch. No tickets. No hand-offs.

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Frequently asked questions

What is CWE-1298?

A hardware race condition occurs when security-critical logic circuits receive signals at slightly different times, creating temporary glitches that can bypass system protections.

How serious is CWE-1298?

MITRE has not published a likelihood-of-exploit rating for this weakness. Treat it as medium-impact until your threat model proves otherwise.

What languages or platforms are affected by CWE-1298?

MITRE lists the following affected platforms: Verilog, VHDL, System on Chip.

How can I prevent CWE-1298?

Adopting design practices that encourage designers to recognize and eliminate race conditions, such as Karnaugh maps, could result in the decrease in occurrences of race conditions. Logic redundancy can be implemented along security critical paths to prevent race conditions. To avoid metastability, it is a good practice in general to default to a secure state in which access is not given to untrusted agents.

How does Plexicus detect and fix CWE-1298?

Plexicus's SAST engine matches the data-flow signature for CWE-1298 on every commit. When a match is found, our Codex Remedium agent opens a fix PR with the corrected code, tests, and a one-line summary for the reviewer.

Where can I learn more about CWE-1298?

MITRE publishes the canonical definition at https://cwe.mitre.org/data/definitions/1298.html. You can also reference OWASP and NIST documentation for adjacent guidance.

Related weaknesses

Weaknesses related to CWE-1298

CWE-362 Parent

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Hardware Logic Contains Race Conditions

What is CWE-1298?

Real-world CVEs caused by CWE-1298

Step-by-step attacker path

Vulnerable Verilog

Secure Verilog

How to prevent CWE-1298

How to detect CWE-1298

Plexicus auto-detects CWE-1298 and opens a fix PR in under 60 seconds.

Frequently asked questions

Weaknesses related to CWE-1298

Concurrent Execution using Shared Resource with Improper Synchronization ('Race Condition')

Race Condition for Write-Once Attributes

Signal Handler Race Condition

Race Condition within a Thread

Time-of-check Time-of-use (TOCTOU) Race Condition

Context Switching Race Condition

Race Condition During Access to Alternate Channel

Permission Race Condition During Resource Copy

Further reading

Don't Let Security
Weigh You Down.

Hardware Logic Contains Race Conditions

What is CWE-1298?

Real-world CVEs caused by CWE-1298

Step-by-step attacker path

Vulnerable Verilog

Secure Verilog

How to prevent CWE-1298

How to detect CWE-1298

Plexicus auto-detects CWE-1298 and opens a fix PR in under 60 seconds.

Frequently asked questions

Weaknesses related to CWE-1298

Concurrent Execution using Shared Resource with Improper Synchronization ('Race Condition')

Race Condition for Write-Once Attributes

Signal Handler Race Condition

Race Condition within a Thread

Time-of-check Time-of-use (TOCTOU) Race Condition

Context Switching Race Condition

Race Condition During Access to Alternate Channel

Permission Race Condition During Resource Copy

Further reading

Don't Let SecurityWeigh You Down.

Don't Let Security
Weigh You Down.