CWE-1318 Base Incomplete

Missing Support for Security Features in On-chip Fabrics or Buses

This vulnerability occurs when the communication channels (fabrics or buses) within a chip lack built-in or enabled security features, such as privilege separation or access controls, leaving data…

Definition

What is CWE-1318?

This vulnerability occurs when the communication channels (fabrics or buses) within a chip lack built-in or enabled security features, such as privilege separation or access controls, leaving data transfers unprotected.
Many on-chip communication systems, especially simpler or low-power designs, are built solely for moving data and lack interfaces to carry critical security attributes like privilege levels or device identity from a master component (like a CPU) to a slave (like a peripheral). Without these dedicated signals, the fabric cannot enforce security policies, making it unsafe for transporting any sensitive security metadata. Even when a bus specification includes optional security signaling, these features are often left unconnected or disabled when the hardware design is generated. Consequently, any peripheral that handles security-sensitive assets should not be connected directly to such a bus unless robust access control is implemented at an earlier point, such as a bridge or intermediary module, before transactions enter the insecure fabric.
Real-world impact

Real-world CVEs caused by CWE-1318

No public CVE references are linked to this CWE in MITRE's catalog yet.

How attackers exploit it

Step-by-step attacker path

  1. 1

    Several systems on chips (SoCs) use the Advanced-Microcontroller Bus Architecture (AMBA) Advanced-Peripheral Bus (APB) protocol. APB is a simple, low-power bus and uses the PPROT[2:0] bits to indicate the security state of the bus masters ;PPROT[0] indicates privilege, PPROT[1] indicates secure/non-secure transaction, and PPROT[2] indicates instruction/data. Assume that there is no fabric bridge in the SoC. One of the slaves, the power-management unit, contains registers that store the thermal-shutdown limits.

  2. 2

    The APB bus is used to connect several bus masters, each with a unique and immutable hardware identity, to several slaves. For a CPU supporting 8 potential identities (each with varying privilege levels), 16 types of outgoing transactions can be made--8 read transactions with each supported privilege level and 8 write transactions with each supported privilege level.

  3. 3

    Since APB PPROT can only support up to 8 transaction types, access-control checks cannot be performed on transactions going to the slaves at the right granularity for all possible transaction types. Thus, potentially, user code running on the CPU could maliciously corrupt the thermal-shutdown-configuration registers to burn the device, resulting in permanent denial of service.

  4. 4

    In this scenario, only peripherals that need access protection from 8 of the 16 possible transaction types can be connected to the APB bus. Peripherals that require protection from the remaining 8 transaction types can be connected to a different APB bus. Alternatively, a bridge could be implemented to handle such complex scenarios before forwarding traffic to the APB bus.

  5. 5

    The Open-Core-Protocol (OCP) fabric supports two configurable, width-optional signals for transporting security attributes: MReqInfo and SRespInfo. MReqInfo is used to transport security attributes from bus master to slave, and SRespInfo is used to transport security attributes from slave to bus master. An SoC uses OCP to connect several bus masters, each with a unique and immutable hardware identity, to several slaves. One of the bus masters, the CPU, reports the privilege level (user or super user) in addition to the unique identity. One of the slaves, the power-management unit, contains registers that store the thermal-shutdown limits.

Vulnerable code example

Vulnerable pseudo

MITRE has not published a code example for this CWE. The pattern below is illustrative — see Resources for canonical references.

Vulnerable pseudo 
// Example pattern — see MITRE for the canonical references.
function handleRequest(input) {
  // Untrusted input flows directly into the sensitive sink.
  return executeUnsafe(input);
}
Secure code example

Secure pseudo

Secure pseudo 
// Validate, sanitize, or use a safe API before reaching the sink.
function handleRequest(input) {
  const safe = validateAndEscape(input);
  return executeWithGuards(safe);
}
What changed: the unsafe sink is replaced (or the input is validated/escaped) so the same payload no longer triggers the weakness.
Prevention checklist

How to prevent CWE-1318

  • Architecture and Design If fabric does not support security features, implement security checks in a bridge or any component that is between the master and the fabric. Alternatively, connect all fabric slaves that do not have any security assets under one such fabric and connect peripherals with security assets to a different fabric that supports security features.
Detection signals

How to detect CWE-1318

Architecture or Design Review High

Review the fabric specification and ensure that it contains signals to transfer security-sensitive signals.

Manual Static Analysis - Source Code High

Lack of security features can also be confirmed through manual RTL review of the fabric RTL.

Plexicus auto-fix

Plexicus auto-detects CWE-1318 and opens a fix PR in under 60 seconds.

Codex Remedium scans every commit, identifies this exact weakness, and ships a reviewer-ready pull request with the patch. No tickets. No hand-offs.

Get a demo Try Plexicus free
Frequently asked questions

Frequently asked questions

What is CWE-1318?

This vulnerability occurs when the communication channels (fabrics or buses) within a chip lack built-in or enabled security features, such as privilege separation or access controls, leaving data transfers unprotected.

How serious is CWE-1318?

MITRE has not published a likelihood-of-exploit rating for this weakness. Treat it as medium-impact until your threat model proves otherwise.

What languages or platforms are affected by CWE-1318?

MITRE lists the following affected platforms: Not OS-Specific, Not Architecture-Specific, Processor Hardware, Not Technology-Specific.

How can I prevent CWE-1318?

If fabric does not support security features, implement security checks in a bridge or any component that is between the master and the fabric. Alternatively, connect all fabric slaves that do not have any security assets under one such fabric and connect peripherals with security assets to a different fabric that supports security features.

How does Plexicus detect and fix CWE-1318?

Plexicus's SAST engine matches the data-flow signature for CWE-1318 on every commit. When a match is found, our Codex Remedium agent opens a fix PR with the corrected code, tests, and a one-line summary for the reviewer.

Where can I learn more about CWE-1318?

MITRE publishes the canonical definition at https://cwe.mitre.org/data/definitions/1318.html. You can also reference OWASP and NIST documentation for adjacent guidance.

Related weaknesses

Weaknesses related to CWE-1318

CWE-693 Parent

Protection Mechanism Failure

This weakness occurs when software either lacks a necessary security control, implements one that is too weak, or fails to activate an…

CWE-1039 Sibling

Inadequate Detection or Handling of Adversarial Input Perturbations in Automated Recognition Mechanism

This vulnerability occurs when a system uses automated AI or machine learning to classify complex inputs like images, audio, or text, but…

CWE-1248 Sibling

Semiconductor Defects in Hardware Logic with Security-Sensitive Implications

A security-critical hardware component contains physical flaws in its semiconductor material, which can cause it to malfunction and…

CWE-1253 Sibling

Incorrect Selection of Fuse Values

This vulnerability occurs when a hardware security fuse is incorrectly programmed to represent a 'secure' state as logic 0 (unblown). An…

CWE-1269 Sibling

Product Released in Non-Release Configuration

This vulnerability occurs when a product ships to customers while still configured with its pre-production or manufacturing settings,…

CWE-1278 Sibling

Missing Protection Against Hardware Reverse Engineering Using Integrated Circuit (IC) Imaging Techniques

This vulnerability occurs when hardware lacks safeguards against physical inspection, allowing attackers to extract sensitive data by…

CWE-1291 Sibling

Public Key Re-Use for Signing both Debug and Production Code

This vulnerability occurs when the same cryptographic key is used to sign both development/debug software builds and final production…

CWE-1319 Sibling

Improper Protection against Electromagnetic Fault Injection (EM-FI)

This vulnerability occurs when a hardware device lacks sufficient shielding against electromagnetic interference, allowing attackers to…

CWE-1326 Sibling

Missing Immutable Root of Trust in Hardware

This vulnerability occurs when a hardware chip lacks a permanent, unchangeable root of trust. Without this immutable foundation, attackers…

Resources

Further reading

Ready when you are

Don't Let Security
Weigh You Down.

Stop choosing between AI velocity and security debt. Plexicus is the only platform that runs Vibe Coding Security and ASPM in parallel — one workflow, every codebase.