CWE-1317: Improper Access Control in Fabric Bridge

Definition

What is CWE-1317?

This vulnerability occurs when a hardware fabric bridge, which connects different IP blocks on a chip, fails to properly verify access permissions for transactions passing through it. The bridge forwards requests without checking the master's privilege level or the hardware identity, effectively bypassing critical security controls.

In modern System-on-Chip (SoC) designs, various Intellectual Property (IP) blocks communicate through a central interconnect bus using different protocols like AHB or OCP. A fabric bridge acts as a translator and router between these blocks. For system security to hold, every transaction's access-control privileges—such as user vs. supervisor mode or secure vs. non-secure identity—must be preserved and enforced as it crosses this bridge. If the bridge is connected to a non-secure fabric or simply forwards transactions without validation, it creates a critical gap. An unauthorized master IP could access restricted slave IPs, or a slave could spoof its identity, leading to privilege escalation, data exposure, or unauthorized control within the chip. Ensuring the bridge actively checks and enforces these controls is essential for maintaining the SoC's security boundaries.

Real-world impact

Real-world CVEs caused by CWE-1317

CVE-2019-6260

Baseboard Management Controller (BMC) device implements Advanced High-performance Bus (AHB) bridges that do not require authentication for arbitrary read and write access to the BMC's physical address space from the host, and possibly the network [REF-1138].

How attackers exploit it

Step-by-step attacker path

1
This example is from CVE-2019-6260 [REF-1138]. The iLPC2AHB bridge connects a CPU (with multiple, privilege levels, such as user, super user, debug, etc.) over AHB interface to an LPC bus. Several peripherals are connected to the LPC bus. The bridge is expected to check the privilege level of the transactions initiated in the core before forwarding them to the peripherals on the LPC bus.
2
The bridge does not implement the checks and allows reads and writes from all privilege levels.
3
To address this, designers should implement hardware-based checks that are either hardcoded to block untrusted agents from accessing secure peripherals or implement firmware flows that configure the bridge to block untrusted agents from making arbitrary reads or writes.
4
The example code below is taken from the AES and core local interrupt (CLINT) peripherals of the HACK@DAC'21 buggy OpenPiton SoC. The access to all the peripherals for a given privilege level of the processor is controlled by an access control module in the SoC. This ensures that malicious users with insufficient privileges do not get access to sensitive data, such as the AES keys used by the operating system to encrypt and decrypt information. The security of the entire system will be compromised if the access controls are incorrectly enforced. The access controls are enforced through the interconnect-bus fabrics, where access requests with insufficient access control permissions will be rejected.
5
The previous code snippet [REF-1382] illustrates an instance of a vulnerable implementation of access control for the CLINT peripheral (see module clint). It also shows a correct implementation of access control for the AES peripheral (see module aes0_wrapper) [REF-1381]. An enable signal (en_o) from the fabric's AXI interface (present in both modules) is used to determine if an access request is made to the peripheral. In the case of the AES peripheral, this en_o signal is first received in a temporary signal en_acct. Then, the access request is enabled (by asserting the en signal) only if the request has sufficient access permissions (i.e., acct_ctrl_i signal should be enabled). However, in the case of the CLINT peripheral, the enable signal, en_o, from the AXI interface, is directly used to enable accesses. As a result, users with insufficient access permissions also get full access to the CLINT peripheral.

Vulnerable code example

Vulnerable Verilog

The example code below is taken from the AES and core local interrupt (CLINT) peripherals of the HACK@DAC'21 buggy OpenPiton SoC. The access to all the peripherals for a given privilege level of the processor is controlled by an access control module in the SoC. This ensures that malicious users with insufficient privileges do not get access to sensitive data, such as the AES keys used by the operating system to encrypt and decrypt information. The security of the entire system will be compromised if the access controls are incorrectly enforced. The access controls are enforced through the interconnect-bus fabrics, where access requests with insufficient access control permissions will be rejected.

Vulnerable Verilog

...
 module aes0_wrapper #(...)(...);
 ...

```
   input logic acct_ctrl_i;
 ...
   axi_lite_interface #(...
   ) axi_lite_interface_i (
   ...
```
.en_o ( en_acct ),** 
  	 ...
 ..);

```
```
assign en = en_acct && acct_ctrl_i;** 
   ...
 endmodule
 ...
 module clint #(...)(...);
 ...

```
   axi_lite_interface #(...
   ) axi_lite_interface_i (
   ...
```
.en_o ( en ),** 
  	 ...
 );
 ...
 endmodule

Secure code example

Secure Verilog

To fix this, enable access requests to CLINT [REF-1383] only if the user has sufficient access as indicated by the acct_ctrl_i signal in the boolean && with en_acct.

Secure Verilog

module clint #(...
 ) (
 ... 

```
```
input logic acct_ctrl_i,** 
   ...
 );

```
   logic en
```
, en_acct** ;
   ...

```
   axi_lite_interface #(...
   ) axi_lite_interface_i (
 ...
   .en_o ( 
```
en_acct**  ),
   ...

```
   );
```
assign en = en_acct && acct_ctrl_i;** 
   ...
 endmodule

What changed: the unsafe sink is replaced (or the input is validated/escaped) so the same payload no longer triggers the weakness.

Prevention checklist

How to prevent CWE-1317

Architecture and Design Ensure that the design includes provisions for access-control checks in the bridge for both upstream and downstream transactions.
Implementation Implement access-control checks in the bridge for both upstream and downstream transactions.

Detection signals

How to detect CWE-1317

Simulation / Emulation High

RTL simulation to ensure that bridge-access controls are implemented properly.

Formal Verification High

Formal verification of bridge RTL to ensure that access control cannot be bypassed.

Frequently asked questions

What is CWE-1317?

This vulnerability occurs when a hardware fabric bridge, which connects different IP blocks on a chip, fails to properly verify access permissions for transactions passing through it. The bridge forwards requests without checking the master's privilege level or the hardware identity, effectively bypassing critical security controls.

How serious is CWE-1317?

MITRE has not published a likelihood-of-exploit rating for this weakness. Treat it as medium-impact until your threat model proves otherwise.

What languages or platforms are affected by CWE-1317?

MITRE lists the following affected platforms: Not OS-Specific, Not Architecture-Specific, Processor Hardware, Not Technology-Specific.

How can I prevent CWE-1317?

Ensure that the design includes provisions for access-control checks in the bridge for both upstream and downstream transactions. Implement access-control checks in the bridge for both upstream and downstream transactions.

How does Plexicus detect and fix CWE-1317?

Plexicus's SAST engine matches the data-flow signature for CWE-1317 on every commit. When a match is found, our Codex Remedium agent opens a fix PR with the corrected code, tests, and a one-line summary for the reviewer.

Where can I learn more about CWE-1317?

MITRE publishes the canonical definition at https://cwe.mitre.org/data/definitions/1317.html. You can also reference OWASP and NIST documentation for adjacent guidance.

Related weaknesses

Weaknesses related to CWE-1317

CWE-284 Parent

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Improper Access Control in Fabric Bridge

What is CWE-1317?

Real-world CVEs caused by CWE-1317

Step-by-step attacker path

Vulnerable Verilog

Secure Verilog

How to prevent CWE-1317

How to detect CWE-1317

Plexicus auto-detects CWE-1317 and opens a fix PR in under 60 seconds.

Frequently asked questions

Weaknesses related to CWE-1317

Improper Access Control

On-Chip Debug and Test Interface With Improper Access Control

Insufficient Granularity of Access Control

Improper Restriction of Write-Once Bit Fields

Improper Prevention of Lock Bit Modification

Security-Sensitive Hardware Controls with Missing Lock Bit Protection

CPU Hardware Not Configured to Support Exclusivity of Write and Execute Operations

Improper Access Control Applied to Mirrored or Aliased Memory Regions

Improper Restriction of Security Token Assignment

Further reading

Don't Let Security
Weigh You Down.

Improper Access Control in Fabric Bridge

What is CWE-1317?

Real-world CVEs caused by CWE-1317

Step-by-step attacker path

Vulnerable Verilog

Secure Verilog

How to prevent CWE-1317

How to detect CWE-1317

Plexicus auto-detects CWE-1317 and opens a fix PR in under 60 seconds.

Frequently asked questions

Weaknesses related to CWE-1317

Improper Access Control

On-Chip Debug and Test Interface With Improper Access Control

Insufficient Granularity of Access Control

Improper Restriction of Write-Once Bit Fields

Improper Prevention of Lock Bit Modification

Security-Sensitive Hardware Controls with Missing Lock Bit Protection

CPU Hardware Not Configured to Support Exclusivity of Write and Execute Operations

Improper Access Control Applied to Mirrored or Aliased Memory Regions

Improper Restriction of Security Token Assignment

Further reading

Don't Let SecurityWeigh You Down.

Don't Let Security
Weigh You Down.